Integrated circuits (IC) are increasing in complexity. The number of devices incorporated within a single IC is greatly increasing and causing the size and complexity of individual ICs to increase. As a result of increased component density and improved fabrication technology is the realization of system on chip (SoC) applications. Such a system on a chip is illustrated in FIG. 1. Core 12 may include many logic and memory functions within it. For example, core 12 may include a CPU core, DSP core, DSP book, memory, control circuitry, and analog/mixed signal circuitry. These are just examples of the types of systems or components that may be integrated into a signal chip 10.
Complexities are associated with the realization of SoC designs. Incorporating diverse components previously contained within a single printed circuit board (PCB) involves confronting many design challenges. The components may be designed for different entities using different tools. Other difficulties lie in fabrication. In general, fabrication processes of memory may differ significantly from those associated with logic circuits. For example, speed may be the priority associated with a logic circuit while current leakage of the stored charge is of priority for memory circuits. Therefore, multi-level interconnect schemes using five to six levels of metal are essential for logic ICs in order to offer improved speed, while memory circuits may need only two to three levels.
Non-planarity or non-planar topology can negatively impact the fabrication of integrated circuits. As devices within integrated circuits decrease in dimension and increase in concentration to property connect these circuits. More complex circuit paths are required. Given the complexity and the number of connections required for this increased number of devices, multiple additional metal level layers are required. Additional metal level layers also require additional insulating layers deposited in between the metal layers. For example, certain current integrated circuit (IC) chips may have up to six (6) levels of metal. Older, larger geometry ICs typically only required a single metal level. These additional layers negatively impact global and local planarity within the IC during fabrication because of the cumulative effect of non-planarity.
Non-planarity may affect etching, deposition, and photo printing processes during IC fabrication. Non-planar topology of multilevel wiring structures can have depth variations of plus or minus 0.5 microns for each metal layers and is cumulative over the entire stack. This depth disparity may reach 1.5 microns or more in a non-planarized structure. At some level of non-planarity etching, deposition, and photo processes result in unacceptably low yields. Photo printing processes are impacted by the non-planar topology as the depth of focus (DOF) will cause imaged patterns to be printed with different dimensions based on the DOF variations caused by the underlying non-planar topology.
One solution to the non-planar problem has been to add additional processing steps that planarize non-planar layers. These processes provide a more planar topology. One such process is chemical mechanical polishing (CMP). CMP is widely during the planarization of dielectric layers used in the fabrication of ICs. Global planarization establishes reliable multilevel metal interconnects and concurrently only be achieved using planarizing processes such as CMP. In CMP, material is removed from the surface of the wafer by a combination of chemical dissolution and abrasion. One of the common problems encountered during CMP arise from a non-uniformity regarding the rate of removing materials. For example, copper may be removed at a higher rate than that of a dielectric or glass. Thus, variations within the concentration of metal patterns may adversely affect global and local planarity.
Glass and metal may respond differently to planarizing processes such as the CMP process, wherein metal, such as copper, may be softer than glass. This may result in the metals being removed at a faster rate than glass. Such removal may result in cupping where the concentration of metal exceeds that of glass. Cupping may adversely affect the planarity of the integrated circuit (IC) and in so doing negatively impact other processes associated with the fabrication of the integrated circuit.
Additionally, large areas within an individual metal layer are often unused. These areas often referred to as “white areas,” are sometimes used for metal fill. Metal filled patterning involves filling large open areas within each metal layer with a metal pattern. These areas may also be used to reroute circuit pathways when blockages in the original pathways occur without the need to completely redraw all metal patterns associated with the IC.